ANALOG LAYOUT ENGINEER- Connect.in

We address the entire breadth ofbusinessneeds, from strategy and design to managing operations. To do this, we draw on deep industry expertise and a command of the fast-evolving fields of cloud, data artificial intelligence, connectivity, software, digital engineering, and platforms.

Capgemini IndiaGo Back

job description

Work independently on block levels analog layout design from Floorplan, Routing and Verifications.

Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,

Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below.

Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.

Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.

Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,

Ability to understand design constraints and implement high-quality layouts.

Multiple Tape out support experience will be an added advantage.

Good people skills and critical thinking abilities to resolve the issue technically, and professionally.

Excellent communication. Responsible for timely execution with high quality of layout design.

Primary Skills

Analog Layout

Process or technology experience:TSMC "â€œ 7nm, 5nm, 10nm,28nm, 45nm,40nm

EDA Tools:

Layout Editor:Cadence Virtuoso L, XL

Physical verification:DRC, LVS, Calibre

Secondary Skills

IO layout

Role: Physical Design / Layout Engineer,

Industry Type: IT Services & Consulting,

Department: Engineering - Hardware & Networks,

Employment Type: Full Time, Permanent

Role Category: Hardware

Education

UG: B.Tech/B.E. in Any Specialization

PG: Any Postgraduate

Key Skills

Skills highlighted with â€˜â€˜ are preferred keyskills

drc analog layout lvs layout design eda tools

circuit dac floorplan routing cadence virtuoso debugging perl cmos adc mixed signal vlsi design eda finfet pvs cadence physical verification pll floor planning serdes pnr synopsys placement vlsi

PHPPerlVLSI Design

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