IBM Processor Architecture and Logic design : Fabric Lead- Connect.in

IBM India Private Limited is the Indiansubsidiaryof IBM. [3] It has facilities in Ahmedabad, Bengaluru, Bhubaneshwar, Chennai, Coimbatore, Delhi, Gurgaon, Hyderabad, Kochi, Kolkata, Mumbai, Noida, Pune, Mysore and Visakhapatnam. Between 2003 and 2007, IBM's head count in India has grown by almost 800%, from 9,000 in 2003 [4] to nearly 74,000 ...

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As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market.

Your Role and Responsibilities

Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor)
Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams
Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature
Signoff the Pre-silicon Design that meets all the functional, area and timing goals
Participate in silicon bring-up and validation of the hardware
Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.
Estimate the overall effort to develop the feature
Estimate the silicon area required for the feature#ISDL_ESD2Q24, #ISAISDLESD24

#ISAISDLESD24

Required Technical and Professional Expertise

8 to 15 years of relevant experience
At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC).
Expertise of SMP coherency
Experience in different on-chip interconnect topologies (e.g., mesh, crossbar)
Understanding of various snoop and data network protocols
Understanding of latency & bandwidth requirements and effective means of implementation
Working knowledge of queuing theory numa/nuca architecture
Proficient in HDLs- VHDL Verilog
Experience in High speed and Power efficient logic design
Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage
Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design
Experience in leading uarch, RTL design teams for feature enhancements.
Follow agile project leadership principles. Work with the team on estimation and execution plan.
Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary.

Requirements : Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

Preferred Technical and Professional Expertise

None

Role: Head - Engineering,

Industry Type: IT Services & Consulting,

Department: Engineering - Software & QA,

Employment Type: Full Time, Permanent

Role Category: Software Development

Education

UG: B.Tech/B.E. in Any Specialization

PG: Any Postgraduate

Key Skills

Skills highlighted with â€˜â€˜ are preferred keyskills

vhdl verilog hdl floor planning logic design

physical design c++digital design design engineering rtl design fpga high level design rtl coding perl system verilog sta art c rtl timing analysis uvm asic design estimation dft fpga design vlsi

C++PHPGitRustPerlLevel DesignASIC Design

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